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Formation of nanosized elements by ion beam lithography for multiple fin field effect transistor prototyping
Author(s): K. A. Tsarik; A. I. Martynov; S. D. Fedotov; V. K. Nevolin
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Paper Abstract

Technique based on FIB and PCE for the formation of nanoscale silicon fins on silicon-on-sapphire structures was demonstrated. The stability of the obtained mask to PCE was investigated depending on the dose of ionic exposure. It was found that the Si fin 150 nm in height and a width of less than 40 nm was obtained by implantation of Ga+ ions with a dose of 3 × 1017 to 4 × 1017 см-2. Current-voltage characteristic of contacts to nanosized fins was researched. The gate dielectric Al2O3 2-3 nm thick was deposited by the ALD method. In the created prototypes of the transistor, the length of each channel was 1.2 μm, and the gate - 100 nm. The obtained I-V characteristics prove the good controllability of the channel in the nanosized fin and demonstrate the operability of the devices.

Paper Details

Date Published: 15 March 2019
PDF: 6 pages
Proc. SPIE 11022, International Conference on Micro- and Nano-Electronics 2018, 110221Q (15 March 2019); doi: 10.1117/12.2522109
Show Author Affiliations
K. A. Tsarik, National Research Univ. of Electronic Technology (Russian Federation)
A. I. Martynov, National Research Univ. of Electronic Technology (Russian Federation)
S. D. Fedotov, National Research Univ. of Electronic Technology (Russian Federation)
Epiel JSC (Russian Federation)
V. K. Nevolin, National Research Univ. of Electronic Technology (Russian Federation)


Published in SPIE Proceedings Vol. 11022:
International Conference on Micro- and Nano-Electronics 2018
Vladimir F. Lukichev; Konstantin V. Rudenko, Editor(s)

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