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Domain specific architectures, hardware acceleration for machine/deep learning
Author(s): Angel I. Solis; Patrica Nava
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Paper Abstract

This article aims to provide the reader with a clear understanding of a subdiscipline in artificial intelligence, Deep Neural Networks. In addition to this, we cover a set of proposed Domain Specific Architectures, Accelerators, that are optimized for these types of computations. In optimizing these computations, we are able to reduce data transfers by keeping data at the processing unit in their individual register files thus increasing energy efficiency per computation.

Paper Details

Date Published: 10 May 2019
PDF: 14 pages
Proc. SPIE 11013, Disruptive Technologies in Information Sciences II, 1101307 (10 May 2019); doi: 10.1117/12.2519554
Show Author Affiliations
Angel I. Solis, The Univ. of Texas at El Paso (United States)
Patrica Nava, The Univ. of Texas at El Paso (United States)


Published in SPIE Proceedings Vol. 11013:
Disruptive Technologies in Information Sciences II
Misty Blowers; Russell D. Hall; Venkateswara R. Dasari, Editor(s)

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