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Information processing via photonic routing: residue number system arithmetic and reconfigurable graph processors (Conference Presentation)
Author(s): Volker J. Sorger; Tarek A. El-Ghazawi
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Paper Abstract

The performance shortcomings of multipurpose compute engines have stirred recent excitement in specialized processors, preempted by GPUs. Simultaneously, computational complexity theory NP ‘hard’ problems scaling as O(n^k) require new hardware solutions. This presents an opportunity for photonic information processors (PIP) building on photonic integration through recent foundry developments. The value proposition for PIPs exist via optical parallelism, small capacitive charging of OE devices, 10’s of ps short propagation delays, a natural convolution via optical interference, and an O(n)-scaling Fourier transform. Based on a recently developed photonic NxN router, here we present two photonic processors; a) the residual arithmetic nanophotonic computer (RANC), and b) a reconfigurable graph processor, the latter being a computing-in-switching (CIS) paradigm. PIPs operate with time-of-flight, once the processor is configured (e.g. setting phase), which is on the order of 10-100 ps given the mm-scale photonic integration footprints. This high bandwidth, however challenges the electronic-optic I/O bottleneck. To address this, we further discuss an optical front-end DAC with <100 ps delay.

Paper Details

Date Published: 14 May 2019
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Proc. SPIE 11013, Disruptive Technologies in Information Sciences II, 110130D (14 May 2019); doi: 10.1117/12.2518755
Show Author Affiliations
Volker J. Sorger, The George Washington Univ. (United States)
Tarek A. El-Ghazawi, The George Washington Univ. (United States)


Published in SPIE Proceedings Vol. 11013:
Disruptive Technologies in Information Sciences II
Misty Blowers; Russell D. Hall; Venkateswara R. Dasari, Editor(s)

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