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Scaling below 3nm node: the 3D CMOS integration paradigm (Conference Presentation)
Author(s): Julien Ryckaert
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Paper Abstract

With the diminishing PPAC returns from dimensional scaling of CMOS technologies, new avenues to maintain the scaling roadmap need to be explored. Design-Technology Co-Optimization has succeeded in leveraging specific integration techniques to alleviate scaling bottlenecks of some critical design rules both in SRAM as well as logic cells. Unfortunately, these building blocks are now reaching records in compactness reducing the amount of integration opportunities to enhance their further scaling. The 3rd dimension has been seen for a long time as a holy grail that could unlock many design constructs bottlenecks in advanced CMOS technology nodes. Many of these attempts have failed in providing a universal solution for CMOS platforms. However, an optimal usage of the 3rd dimension can be found in some specific cases by a careful understanding of the design context. We will review in this talk few 3D CMOS integration techniques that offer new scaling opportunities for future technology nodes. Among these approaches we will explore the usage of buried interconnects for power delivery, the use of vertically oriented FETs for on-chip memory as well as a disruptive device built out of the stack of a pFET and an nFET into a single structure called CFET. In the latter, we will explore its scaling potential as a means to position it as a future general purpose device solution for CMOS logic as well as SRAM.

Paper Details

Date Published: 18 March 2019
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Proc. SPIE 10963, Advanced Etch Technology for Nanopatterning VIII, 109630O (18 March 2019); doi: 10.1117/12.2517767
Show Author Affiliations
Julien Ryckaert, IMEC (Belgium)


Published in SPIE Proceedings Vol. 10963:
Advanced Etch Technology for Nanopatterning VIII
Richard S. Wise; Catherine B. Labelle, Editor(s)

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