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Fast detection of largest repeating layout pattern
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Paper Abstract

Several tools in the mask data preparation flow utilize the repetitions of patterns within a layout to reduce processing time. Conventionally, this is achieved by an analysis of the design hierarchy. However, intermediate processing in the data preparation flow can distort the hierarchy. Also, some repetitions in small-grain structures may not be represented in the hierarchy. An alternative is to learn repeating patterns and their frequency by analyzing the layout as a flat data structure. This paper demonstrates a methodology for learning the largest repeating patterns in a layout without the use of hierarchy, purely by referencing the layout as a flat data structure. The experimental results show its efficacy for layouts containing hundreds of thousands of polygons, as well as its efficiency in terms of computing time and memory usage. The results indicate that it is practical to use a distributed process to directly learn the largest repeating patterns without resorting to design hierarchy, in a reasonable runtime and memory usage.

Paper Details

Date Published: 20 March 2019
PDF: 12 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620A (20 March 2019); doi: 10.1117/12.2517194
Show Author Affiliations
Jingsong Chen, The Chinese Univ. of Hong Kong (Hong Kong, China)
James Shiely, Synopsys Inc. (United States)
Evangeline F. Y. Young, The Chinese Univ. of Hong Kong (Hong Kong, China)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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