Share Email Print
cover

Proceedings Paper • new

SALELE process from theory to fabrication
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

For many years, the preservation of Moore’s law has been achieved by the means of Multi Pattering Technologies (MP) and Immersion lithography. Starting from the 7nm technology node, the Era of EUV mass production started to play a fundamental role in semiconductor manufacturing industry. However, EUV Direct printing comes with lots of challenges, especially at small pitches and tight tip-to-tip spacing. The combination between MP and EUV technologies will be the key factor in Moore’s law continuity in advanced nodes. Hence, this will enable Critical Dimension’s (CD) scaling down, and accordingly increases chips’ density, and provides more computational power chips. IMEC’s iN5 technology node, equivalent to industrial N3 technology node, uses SALELE Process to get critical features with tight tip-to-tip spacing in Back-End-Of-Line layers. SALELE process combines the two main MP approaches: (a) Self-Aligned MP and (b) Litho-Etch/Litho-Etch MP along with EUV technology. This combination creates a patterning methodology that overcomes EUV direct printing limitations and potentially creates a path towards scaling down. In this work we are introducing a manufacturing flow for the SALELE Process in details. Starting with layout decomposition, where the drawn layer is decomposed into 4 Masks: 2 Metal-like Masks, and 2 Block-like Masks. Then each of these masks is subjected to Optical Proximity Correction (OPC) process, and here we explain more about the OPC recipe development for each mask. Then we introduce a verification flow that performs two levels of verifications: (a) Litho verification, where the litho fidelity of each mask is quantified based on image quality measurements. (b) Final Manufactured shapes verification vs. expected output. This work has been carried out on an N3 candidate layout designed by IMEC.

Paper Details

Date Published: 21 March 2019
PDF: 12 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620V (21 March 2019); doi: 10.1117/12.2517051
Show Author Affiliations
Youssef Drissi, IMEC (Belgium)
Werner Gillijns, IMEC (Belgium)
Jae Uk Lee, IMEC (Belgium)
Ryan Ryoung han Kim , IMEC (Belgium)
Ahmed Hamed-Fatehy, Mentor Graphics Egypt (Egypt)
Rehab Kotb, Mentor Graphics Egypt (Egypt)
Rajiv Naresh Sejpal, Mentor Graphics Corp. (Belgium)
Germain Fenger, Mentor Graphics Corp. (United States)
James Word, Mentor Graphics Corp. (United States)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

© SPIE. Terms of Use
Back to Top