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Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)
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Paper Abstract

Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.

Paper Details

Date Published: 26 March 2019
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Proc. SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 109591U (26 March 2019); doi: 10.1117/12.2516613
Show Author Affiliations
Cyrus E. Tabery, ASML US, Inc. (United States)
Vito Rutigliani, IMEC (Belgium)
Simon Hastings, ASML US (United States)
Etienne de Poortere, ASML US (United States)
Luke Wang, Hermes Microvision, Inc. (United States)
Philippe Leray, IMEC (Belgium)
Guillaume Schelcher, IMEC (Belgium)
Yongjun Wang, ASML US (United States)


Published in SPIE Proceedings Vol. 10959:
Metrology, Inspection, and Process Control for Microlithography XXXIII
Vladimir A. Ukraintsev; Ofer Adan, Editor(s)

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