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Pattern-aware diagnostics: using high-performance pattern analysis to identify defect root cause (Conference Presentation)
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Paper Abstract

Layout-pattern-based approaches for physical design analysis and verification have become mainstream in recent years and are enabling many new applications. Prior work introduced the ability to collect all patterns from multiple layouts into a catalog as well as to use machine learning techniques to score and filter patterns to identify which ones are critical. In this paper, data mined from a library of scored patterns from established designs is applied to the analysis of diagnosis results from a new design to improve defect root cause analysis (RCA). The flow for this approach is as follows: patterns interacting with nets reported in diagnosis callouts are selected as patterns of interest (POIs) from the catalog of all patterns. Next, features of interest (FOIs) are extracted from all POIs to build a dataframe. Finally, volume diagnosis results identifying nets with likely open or short defects are added to the dataframe. RCA is performed using the dataframe to identify likely root cause(s) for failures and suggest refined failure locations for targeted inspection, physical failure analysis, or other electrical failure analysis. The approach described above is applied to products in high-volume manufacturing using a leading-edge technology node. Silicon validation results will be included for example applications.

Paper Details

Date Published: 18 March 2019
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Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096209 (18 March 2019); doi: 10.1117/12.2516571
Show Author Affiliations
Jason P. Cain, Advanced Micro Devices, Inc. (United States)
Abdullah Yassine, Advanced Micro Devices, Inc. (United States)
Moutaz Fakhry, Advanced Micro Devices, Inc. (United States)
Piyush Pathak, Cadence Design Systems, Inc. (United States)
Jeffrey E. Nelson, Cadence Design Systems, Inc. (United States)
Frank Gennari, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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