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LCDU improvement of EUV-patterned vias with DSA
Author(s): Jing Guo; Dustin W. Janes; Yann Mignot; Richard C. Johnson; Cheng Chi; Chi-Chun Liu; Luciana Meli; Takuya Kuroda; Domenico A. DiPaola; Yuji Tanaka; Harumoto Masahiko; Nelson M. Felix; Daniel A. Corliss
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Paper Abstract

Lithographic and pitch-multiplying spacer technologies are widely used to shrink interconnect periodicity within critical layers. This places significant burden on overlay and CD uniformity of the subsequently patterned vias to physically contact and electrically connect critical layers to the rest of the integrated circuit in a nearly defect-free and perfectly-consistent manner. We are evaluating the combination of EUV and DSA patterning technologies to meet this challenge and enable future technology nodes. The contact hole guide pattern is fabricated atop bilayer hardmask material by single-exposure EUV, surface-modified with telechelic polymer brush materials, and finally shrunk/rectified using self-assembled, lamella-forming polystyrene-block-polymethylmethacrylate (PS-b-PMMA). The nascent via pattern is then blanket exposed by DUV light and the photolyzed PMMA is selectively rinsed away. Here we study the process performance of DSA pattern wet etch chemistry and subsequent dry etch pattern transfer into bilayer hardmask material using both metrology and electrical yield measurements as evaluation criteria. In particular, the choice of wet etch solvation strength selective towards PMMA was varied from moderate (isopropanol, IPA) to good (acetic acid, AAc). Due to the ability of AAC to solubilize all covalently-untethered PMMA, regardless of molecular weight, the resulting average CD is wider and its local distribution is more uniform. In contrast, IPA is only capable of rinsing away the smallest PMMA fragments, resulting in relatively tighter bounds about the preferable blanket UV dose, and a smaller average CD and less-uniform local CD distribution. These morphological differences are confirmed by cross-sectional transmission electron micrographs. Brightfield inspection and inline electrical testing are used to compare relative defectivity and yield, respectively, to assess the potential impact on device performance for processes utilizing either solvent.

Paper Details

Date Published: 26 March 2019
PDF: 11 pages
Proc. SPIE 10958, Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019, 109580N (26 March 2019); doi: 10.1117/12.2515153
Show Author Affiliations
Jing Guo, IBM Research–Albany NanoTechnology (United States)
Dustin W. Janes, SCREEN SPE USA, LLC (United States)
Yann Mignot, IBM Research–Albany NanoTechnology (United States)
Richard C. Johnson, IBM Research–Albany NanoTechnology (United States)
Cheng Chi, IBM Research–Albany NanoTechnology (United States)
Chi-Chun Liu, IBM Research–Albany NanoTechnology (United States)
Luciana Meli, IBM Research–Albany NanoTechnology (United States)
Takuya Kuroda, SCREEN SPE USA, LLC (United States)
Domenico A. DiPaola, SCREEN SPE USA, LLC (United States)
Yuji Tanaka, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Harumoto Masahiko, SCREEN Semiconductor Solutions Co., Ltd. (Japan)
Nelson M. Felix, IBM Research–Albany NanoTechnology (United States)
Daniel A. Corliss, IBM Research–Albany NanoTechnology (United States)


Published in SPIE Proceedings Vol. 10958:
Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019
Martha I. Sanchez; Eric M. Panning, Editor(s)

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