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Topography and flatness induced overlay distortion correction using resist drop pattern compensation in nanoimprint lithography systems
Author(s): Anshuman Cherala; Se-Hyuk Im; Mario Meissl; Ahmed Hussein; Logan Simpson; Ryan Minter; Ecron Thompson; Jin Choi; Mitsuru Hiura; Satoshi Iino
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Paper Abstract

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid, which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Overlay budgets play a large role in defining production readiness. As an example, DRAM devices require overlay on the order of 20% of the half pitch. Canon uses a through the mask (TTM) alignment system to measure a Moiré image anywhere in the field. This system can also record alignment errors of all fields and all marks. The data collected by the TTM system correlates very closely with an Archer measurement tool. In addition, a High Order Distortion Correction (HODC) system, which applies a heat input on a field by field basis through the use of a DMD array has been combined with magnification actuators to correct high order distortion terms up to K30. There is an additional distortion term that must also be addressed for the case of nanoimprint lithography. NIL drop patterns are typically designed to minimize resist fill time and create a uniform residual layer beneath the resist pattern. For device wafers, however, it is important to recognize that there are both long wavelength flatness errors coming from the wafer chuck and existing pattern topography from previously patterned levels that cause out of plane errors. When the mask comes in contact with the resist on the wafer, these out of plane errors can then induce mask bending, resulting in an additional distortion term. To minimize this distortion, a Drop Pattern Compensation (DPC) Model has been implemented to minimize the added distortion terms. In this paper we describe the origins of the out of plane errors, and describe the model used to correct these errors along with some examples. Finally, results are presented for a device like wafer in which the overlay errors within a field are reduced from 5.4nm to 3.4nm, 3 sigma.

Paper Details

Date Published: 16 May 2019
PDF: 9 pages
Proc. SPIE 10958, Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019, 109580C (16 May 2019); doi: 10.1117/12.2515146
Show Author Affiliations
Anshuman Cherala, Canon Nanotechnologies, Inc. (United States)
Se-Hyuk Im, Canon Nanotechnologies, Inc. (United States)
Mario Meissl, Canon Nanotechnologies, Inc. (United States)
Ahmed Hussein, Canon Nanotechnologies, Inc. (United States)
Logan Simpson, Canon Nanotechnologies, Inc. (United States)
Ryan Minter, Canon Nanotechnologies, Inc. (United States)
Ecron Thompson, Canon Nanotechnologies, Inc. (United States)
Jin Choi, Canon Nanotechnologies, Inc. (United States)
Mitsuru Hiura, Canon Inc. (Japan)
Satoshi Iino, Canon Inc. (Japan)


Published in SPIE Proceedings Vol. 10958:
Novel Patterning Technologies for Semiconductors, MEMS/NEMS, and MOEMS 2019
Martha I. Sanchez; Eric M. Panning, Editor(s)

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