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Backside power delivery as a scaling knob for future systems
Author(s): Bharani Chava; Khaja Ahmad Shaik; Anne Jourdain; Sofiane Guissi; Pieter Weckx; Julien Ryckaert; Geert Van Der Plaas; Alessio Spessot; Eric Beyne; Anda Mocuta
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Paper Abstract

Standard cell track height scaling provides us with sufficient area scaling at the standard cell library level. The efficiency of this technique and the complexities involved with this scaling method have been discussed in detail [1,2]. However, the area benefits of standard cell track height scaling diminish when we consider the complexities of incorporating on-chip power grid into the DTCO exploration loop. We have previously outlined several layout techniques to improve the utilization density of this scaling technology [2,4]. However, the proposed techniques only minimize the impact of the power grid on the design. In this work, we discuss the need to combine 3D – μTSV technology and logic technology to decouple the power grid from the design budget. The proposed technique delivers power from the backside of a thinned device wafer using the process steps depicted in Figure 4. Our analysis demonstrates significant area savings and IR-drop reduction. We use SPICE simulations to extract grid resistances as part of our technology targeting process, based upon a high-level on-chip PDN model. We also verify our findings using a commercially available EDA toolchain.

Paper Details

Date Published: 20 March 2019
PDF: 6 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096205 (20 March 2019); doi: 10.1117/12.2514942
Show Author Affiliations
Bharani Chava, IMEC (Belgium)
Khaja Ahmad Shaik, IMEC (Belgium)
Anne Jourdain, IMEC (Belgium)
Sofiane Guissi, IMEC (France)
Pieter Weckx, IMEC (Belgium)
Julien Ryckaert, IMEC (Belgium)
Geert Van Der Plaas, IMEC (Belgium)
Alessio Spessot, IMEC (Belgium)
Eric Beyne, IMEC (Belgium)
Anda Mocuta, IMEC (Belgium)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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