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Design rule exploration for width sensitive zone for metal layers in advanced nodes
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Paper Abstract

Use of lithography exposure and metrology tools in production typically results in worse performance than seen on test wafers. Physical design always starts with rough design rule for a new technology node. To evaluate the influence of the inevitable degraded performance on test wafers, our paper put forward a systematic approach to evaluate whether the ability of current process can support the design. The approach utilizes litho-friendly design (LFD) to find the yield killers and conducts pattern classification with pattern matching. Process window discovery (PWD) is used to collect the statistical data to confirm whether the yield killers in LFD simulation will meet the systematic fail on wafer. It is necessary to do mask optimization (MO), source mask optimization (SMO) and design rule optimization (DRO) for the real yield killers. Moreover, design of advanced node may include the patterns inside forbidden pitch range. We do the design rule exploration for metal 2 layer of 14nm technology node and discuss the corresponding solutions for width sensitive zone as well.

Paper Details

Date Published: 20 March 2019
PDF: 11 pages
Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096212 (20 March 2019); doi: 10.1117/12.2514783
Show Author Affiliations
Xiaojing Su, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)
Lisong Dong, Institute of Microelectronics (China)
Yayi Wei, Institute of Microelectronics (China)
Univ. of Chinese Academy of Sciences (China)
Yajuan Su, Institute of Microelectronics (China)
Rui Chen, Institute of Microelectronics (China)
Chunshan Du, Mentor Graphics Corp. (China)


Published in SPIE Proceedings Vol. 10962:
Design-Process-Technology Co-optimization for Manufacturability XIII
Jason P. Cain, Editor(s)

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