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Proceedings Paper

Efficient VLSI architecture for block-matching motion estimation
Author(s): Han Kyu Lee; Jinwoong Kim; Young-Mi Ohk; Kangwhan Lee
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Paper Abstract

Motion estimation reduces temporal redundancies in a video sequence, and becomes the most demanding part in video source encoders where motion compensated transform coding method is used. Block matching algorithm needs a large amount of computational load, but its regular data flow structure is good to implement with various parallel processing architectures. In this paper, we present a new VLSI architecture for block matching motion estimation in video encoding systems. The proposed architecture is based on linear systolic arrays. The proposed architecture has (1) fully pipelining operation which achieves 100 percent efficiency of processing elements, (2) efficient data input scheme for high input-rate video encoding systems, (3) glueless interfaces for easy extension of search range by cascaded multiple chip connections, (4) very regular and modular structure which is good to ASIC implementation.

Paper Details

Date Published: 16 September 1996
PDF: 7 pages
Proc. SPIE 2952, Digital Compression Technologies and Systems for Video Communications, (16 September 1996); doi: 10.1117/12.251322
Show Author Affiliations
Han Kyu Lee, Electronic and Telecommunications Research Institute (South Korea)
Jinwoong Kim, Electronic and Telecommunications Research Institute (South Korea)
Young-Mi Ohk, Electronic and Telecommunications Research Institute (South Korea)
Kangwhan Lee, Kimchon College (South Korea)


Published in SPIE Proceedings Vol. 2952:
Digital Compression Technologies and Systems for Video Communications
Naohisa Ohta, Editor(s)

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