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Analysis and modelling of patterned wafer nano-topography using multiple linear regression on design GDS and silicon PWG data
Author(s): M. Kessar; B. Le-Gratiet; P. Lemaire; V. Brouzet; D. Le Cunff; V. Gredy
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Paper Abstract

Every nanometer of residual nano-topography (with high spatial frequency fingerprint) that the scanner cannot correct during the wafer exposure directly propagates into the focus budget [1].

Process windows are getting tight with a greater and greater contribution of the focus budget. Nanotopography is highly correlated to the chip layout. As a consequence it shows systematic peaks and valleys shifting locally optimum process conditions. Mean, standard deviations and ranges are not enough to characterize it.

It is of high importance to know topography maps to identify care areas on silicon with high risks of defocus situations [2]. These maps can be measured at any process step using PWG (Patterned Wafer Geometry) tools but could also be predicted with models (see proof of concept [3]).

The first part of this paper deals with the development of scripts to extract and express in multiples ways topography information. Different types of expressions will be shown followed by two use cases related to topography description situation: striation detection and slurry choice for CMP. Those two use cases are proofs of concepts showing that data valorization is a path to provide information that can help process engineers to make decisions and save time for defect detection.

This paper ends with a deeper exploration of the correlations between chip designs and nanotopography from an image processing point of view (design layout and wafer topography maps). Short-range and long-range contributions of layouts are used to model nano-topography through a multiple linear regression [4] of the pre-processed design layers densities (surface and perimeter) and wafer topography which is characterized in this work using KLA PWG tooling. The goal being here to predict wafer topography before silicon is being processed so that mitigation solutions can be set up.

PWG metrology tool can measure a full wafer nano-topography map with pixels size of 100μm*100μm which is enough for a focus analysis. Results show that the first model version reaches encouraging figures of 0.77 R2 for a product layer having a 20nm topography range.

Paper Details

Date Published: 26 March 2019
PDF: 8 pages
Proc. SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 109592Q (26 March 2019); doi: 10.1117/12.2512398
Show Author Affiliations
M. Kessar, STMicroelectronics S.A. (France)
Univ. Grenoble Alpes, CNRS, Grenoble Institute of Engineering Univ. (France)
B. Le-Gratiet, STMicroelectronics S.A. (France)
P. Lemaire, Univ. Grenoble Alpes, CNRS, Grenoble Institute of Engineering Univ. (France)
V. Brouzet, STMicroelectronics S.A. (France)
D. Le Cunff, STMicroelectronics S.A. (France)
V. Gredy, STMicroelectronics S.A. (France)


Published in SPIE Proceedings Vol. 10959:
Metrology, Inspection, and Process Control for Microlithography XXXIII
Vladimir A. Ukraintsev; Ofer Adan, Editor(s)

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