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Challenges and solutions for high-speed integrated silicon photonics
Author(s): Thomas Y. L. Ang; Jun Rong Ong; Soon Thor Lim; Ching Eng Png
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Paper Abstract

The compatibility of silicon photonics with existing CMOS fabrication processes enables the possibility of large scale manufacturing of integrated photonics for communication applications above 100Gbit/s. However, the design of silicon photonics devices that are able to fulfil the high-performance requirements of broad optical bandwidth ( 50nm), low loss (2dB), high-speed (25Gbit/s), low driving voltage (≥ –5V), large fabrication tolerance (±20nm) and high reproducibility across the wafer is a unique practical challenge. In this work, we present a library of passive and active integrated silicon photonic devices that meet the stringent design requirements for communication applications. The design, modelling and experimental results are presented for low loss edge couplers with insertion loss < 2dB, low-loss waveguides and bends, high-performance polarization beam splitter with extinction ratio above 25 dB, broadband directional couplers with optical bandwidth above 50nm, and arrayed waveguide gratings (AWGs) with low insertion loss < 1dB. Last but not least, high-speed silicon modulators (25Gbit/s) with phase efficiency VπL ≤ 2V.cm at DC reverse bias of ≥ –5V and low propagation loss of ≤ ∼1dB/mm are demonstrated.

Paper Details

Date Published: 14 March 2019
PDF: 9 pages
Proc. SPIE 10923, Silicon Photonics XIV, 1092306 (14 March 2019); doi: 10.1117/12.2509470
Show Author Affiliations
Thomas Y. L. Ang, A*STAR Institute of High Performance Computing (Singapore)
Jun Rong Ong, A*STAR Institute of High Performance Computing (Singapore)
Soon Thor Lim, A*STAR Institute of High Performance Computing (Singapore)
Ching Eng Png, A*STAR Institute of High Performance Computing (Singapore)


Published in SPIE Proceedings Vol. 10923:
Silicon Photonics XIV
Graham T. Reed; Andrew P. Knights, Editor(s)

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