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Proceedings Paper

Tungsten plug contact and via integration for subhalf-micron technology
Author(s): Harianto Wong; Chetlur S. Sreekanth; Lap Hung Chan
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Paper Abstract

Tungsten plug technology has been used extensively for multilevel interconnect in sub-half-micron semiconductor processes. The major issue encountered in tungsten plug integration is contact resistance especially to the p+ Si area and via resistance. In this study, investigations were carried out on several aspects of contact cleaning, plug implant, and barrier metal deposition. The test vehicle utilized is in-house logic test chip with 0.35 micrometers design rule. Contact resistance of tungsten plug was found to be strongly correlated with contact cleaning, plug implant and Ti deposition thickness. Ar sputter clean was shown to have detrimental effect towards contact and via resistances. Plug implant was shown to be a necessary step for p+ contact resistance control. Thicker Ti deposition was also shown to be crucial in improving contact resistance.

Paper Details

Date Published: 13 September 1996
PDF: 11 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250886
Show Author Affiliations
Harianto Wong, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Chetlur S. Sreekanth, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Lap Hung Chan, Chartered Semiconductor Manufacturing Ltd. (Singapore)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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