Share Email Print
cover

Proceedings Paper

Interconnection schemes for parasitics optimization
Author(s): Nicolas Delorme; Marc Belleville; Sylvette Bisotto; Jean Chilo
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance technology performance. These strategies consist in: increasing the inter-metal dielectric thicknesses, using SiOF instead of SiO2, embedding the interconnects in a low-permittivity dielectric and switching to copper metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures, for delay, crosstalk, and consumption in standard circuit routings, and for a 32 bits adder worst case delay and consumption.

Paper Details

Date Published: 13 September 1996
PDF: 12 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250885
Show Author Affiliations
Nicolas Delorme, LETI-CEA/Grenoble (France)
Marc Belleville, LETI-CEA/Grenoble (France)
Sylvette Bisotto, LETI-CEA/Grenoble (France)
Jean Chilo, LEMO-UMR (France)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

© SPIE. Terms of Use
Back to Top