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Proceedings Paper

Copper metallization for on-chip interconnects
Author(s): A. V. Gelatos; Bich-Yen Nguyen; Kathleen A. Perry; R. Marsh; J. Peschke; Stanley M. Filipiak; Edward O. Travis; Matthew A. Thompson; T. Saaranen; Phil J. Tobin; C. J. Mogab
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Paper Abstract

Continued dimensional scaling of the elements of integrated circuits places significant restrictions on the width, density and current carrying capability of metallic interconnects. It is expected that, by the year 2000, the transistor channel length will be at 0.l8piri [1], while microprocessors will pack more than 15 million transistors over an area of '-700mm2. To conserve area, interconnects will continue to be stacked at an increasing number of levels (6 by the year 2000, vs 4 in todays leading microprocessors) and the minimum spacing and width within an interconnect layer will shrink to 0.3.tm. In addition, it is expected that future interconnects will need to sustain increasingly higher current densities without electromigration failures [2]. Aluminum alloys are the conductors of choice in present-day interconnects, and much effort is focused n means to extend the usefulness of aluminum through improvements in reliability, either by new alloy formulations [3], or by the development of complicated multimetal stacks [4. A more radical approach, which is gaining increased attention, is the replacement of aluminum altogether by copper. The bulk resistivity of copper is significantly lower than that of aluminum (1.7.tW-cm for Cu vs. 3.0iW-cm for Al-Cu), which is expected to translate to interconnects of higher performance because of reduction in signal propagation delay. In addition, the significantly higher melting temperature of copper (.-1100°C vs. -600°C for Al-Cu alloys) and its higher atomic weight are expected to translate to improved resistance to electromigration [5]. However, as with any new process trying to break into the mainstream, significant improvement in reliability and performance over that achievable with aluminum alloys must be demonstrated first. Towards this purpose, processes need to be developed that deposit conformal copper films of high purity with acceptable throughput, and integration schemes need to be developed which produce interconnects and multilevel metal structures with reliability significantly better than that of aluminum. This article describes our efforts to integrate copper in the backend of integrated circuits. The first part deals with the chemical vapor deposition (CVD) of copper films. The second describes the integration of copper into the last metal level of a 2-level metal 0.5um BiCMOS SRAM circuit.

Paper Details

Date Published: 13 September 1996
PDF: 12 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250884
Show Author Affiliations
A. V. Gelatos, Motorola (United States)
Bich-Yen Nguyen, Motorola (United States)
Kathleen A. Perry, Motorola (United States)
R. Marsh, Applied Materials (United States)
J. Peschke, Motorola (United States)
Stanley M. Filipiak, Motorola (United States)
Edward O. Travis, Motorola (United States)
Matthew A. Thompson, Motorola (United States)
T. Saaranen, Motorola (United States)
Phil J. Tobin, Motorola (United States)
C. J. Mogab, Motorola (United States)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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