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Proceedings Paper

Trench isolation technology for high-performance complementary bipolar devices
Author(s): Kevin C. Brown; Chris Bracken; Rashid Bashir; Kulwant Egan; Joe DeSantis; Abul Ehsanul Kabir; Wipawan Yindeepol; Joel McGregor; S. J. Prasad; Reda Razouk; Victor V. Boksha; Juan C. Rey
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Paper Abstract

A trench isolation architecture for a low voltage (< 15 V), high frequency, complementary bipolar process technology has been developed. This technology features shallow and deep trench isolation with a minimum design rule of 1.0 (mu) , along with a zero encroachment deposited field oxide. Trench etch process results suggest a mechanism whereby, depending on the amount of exposed silicon, the plasma can either be considered `silicon deficient' or `oxygen deficient.' Black silicon formation during trench etching has been eliminated with an in-situ removal of the photoresist after the hardmask oxide has been defined. Terrain isolation process simulation results are shown to be more accurate in depicting actual wafer processing structures than Tsuprem-4. Initial bipolar device characteristics are reported that illustrate the integration of the introduced PlaTOx device isolation architecture. Realized ft/fmax are 6.3/9.5 GHz for NPN, and 3.8/8.2 GHz for PNP transistors.

Paper Details

Date Published: 13 September 1996
PDF: 14 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250883
Show Author Affiliations
Kevin C. Brown, National Semiconductor Corp. (United States)
Chris Bracken, National Semiconductor Corp. (United States)
Rashid Bashir, National Semiconductor Corp. (United States)
Kulwant Egan, National Semiconductor Corp. (United States)
Joe DeSantis, National Semiconductor Corp. (United States)
Abul Ehsanul Kabir, National Semiconductor Corp. (United States)
Wipawan Yindeepol, National Semiconductor Corp. (United States)
Joel McGregor, National Semiconductor Corp. (United States)
S. J. Prasad, National Semiconductor Corp. (United States)
Reda Razouk, National Semiconductor Corp. (United States)
Victor V. Boksha, Technology Modeling Associates (United States)
Juan C. Rey, Technology Modeling Associates (United States)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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