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Proceedings Paper

Study of integration issues in shallow trench isolation for deep submicron CMOS technologies
Author(s): Amitava Chatterjee; Mark E. Mason; K. Joyner; Daty Rogers; Doug Mercer; John Kuehne; A. L. Esquivel; P. Mei; Suhail S. Murtaza; Kelly J. Taylor; Iqbal Ali; S. Nag; Sean C. O'Brien; S. Ashburn; Ih-Chin Chen
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Paper Abstract

This paper presents a study of the issues in integrating the pattern, fill, planarization and surface cleanup processes to design a shallow trench isolation (STI) flow suitable for 0.25 micrometers CMOS technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data is presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.

Paper Details

Date Published: 13 September 1996
PDF: 9 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250874
Show Author Affiliations
Amitava Chatterjee, Texas Instruments Inc. (United States)
Mark E. Mason, Texas Instruments Inc. (United States)
K. Joyner, Texas Instruments Inc. (United States)
Daty Rogers, Texas Instruments Inc. (United States)
Doug Mercer, Texas Instruments Inc. (United States)
John Kuehne, Texas Instruments Inc. (United States)
A. L. Esquivel, Texas Instruments Inc. (United States)
P. Mei, Texas Instruments Inc. (United States)
Suhail S. Murtaza, Texas Instruments Inc. (United States)
Kelly J. Taylor, Texas Instruments Inc. (United States)
Iqbal Ali, Texas Instruments Inc. (United States)
S. Nag, Texas Instruments Inc. (United States)
Sean C. O'Brien, Texas Instruments Inc. (United States)
S. Ashburn, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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