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Proceedings Paper

Pass transistor and isolation design methodology and its implementation for improved manufacturability for 256-Mbit DRAM and beyond
Author(s): Amitava Chatterjee; Mark Rodder; Ih-Chin Chen
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Paper Abstract

With the active area pitch being pushed to the limit of LOCOS isolation, manufacturability of the array transistor is increasingly affected by the isolation design. In this paper we have enhanced our design for manufacturability methodology to include the effects of isolation design in addition to those of transistor design. We apply this methodology to 256 Mbit DRAM and demonstrate a margin of 0.06 micrometers for both nitride width (W) and poly gate length (Lg) variations for an isolation pitch of 0.6 micrometers and target Lg of 0.25 micrometers . This margin is obtained with Sidewall-Sealed MSL SSMSL process without edge oxide and using a heavy dose of channel stop implant. The diode leakage and gate oxide integrity are shown to be within acceptable limits. In terms of transistor design, pocket implanted transistors are shown to be marginally better than conventional transistors due to larger margin for Lg variation and comparable diode leakage.

Paper Details

Date Published: 13 September 1996
PDF: 5 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250871
Show Author Affiliations
Amitava Chatterjee, Texas Instruments Inc. (United States)
Mark Rodder, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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