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Proceedings Paper

Scalability of conventional and sidewall-sealed LOCOS technology for 256-Mbit DRAM array and periphery isolation
Author(s): Mark Rodder; Jeong-Mo Hwang; Ih-Chin Chen
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Paper Abstract

LOCOS technology is being investigated for applicability to 256 Mbit DRAM applications in the memory array (with active region pitch < 0.6 micrometers ) as well as the periphery. In this paper, LOCOS isolation is demonstrated for array n--n- spacing < 0.2 micrometers for 256 Mbit DRAM array and for n+-n+ (and p+-p+) spacing < 0.35 micrometers for DRAM periphery. Array nMOSFETs with small active width of 0.2 micrometers are demonstrated with Ioff < lfA/micrometers (VB equals IV) at Lo equals 0.2 micrometers while maintaining low VT (<VTspec equals 1.5 V at VB equals 4 V) at Lo equals 0.3 micrometers in accordance with DRAM pass transistor design. These key results are obtained with appropriate LDD dose and energy, sidewall sealed LOCOS isolation, and 1100 degree(s)C field oxidation to reduce both field oxide thinning and active width encroachment. MOSFETs with sidewall sealed LOCOS show small narrow width effect, (Delta) VT/(Delta) W, and no sub-VT `double-hump'. In contrast, conventional LOCOS results in high (Delta) VT/(Delta) W for MOSFETs with active width < 0.4 micrometers while recessed LOCOS causes sub- VT `double-hump' for large active width MOSFETs.

Paper Details

Date Published: 13 September 1996
PDF: 8 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250870
Show Author Affiliations
Mark Rodder, Texas Instruments Inc. (United States)
Jeong-Mo Hwang, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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