Share Email Print
cover

Proceedings Paper

Gate oxide field design in the sub-10-nm region
Author(s): Katsuhiko Kubota; C. Suzuki; Kosuke Okuyama; N. Suzuki
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper discusses the gate oxide fields for MOS LSI design in the sub-10 nm gate oxide region for the nearest next few generations. Since practical determination of allowable gate oxide fields for scaled gate oxides strongly depends on oxide defect density levels, we measured defect densities for gate oxide thicknesses down to 3 nm. The defect-related breakdown failures affecting reliability were found to decrease with decreasing gate oxide thickness. The allowable gate oxide fields were calculated as a function of the gate oxide thickness and gate area to meet reliability criteria. The discussion also includes recent key issues such as the contribution of high-quality wafer substrates to allowable electric fields, and design guidelines for dual power supply voltages. Since the defect density levels depend on process, we generalized our discussion by showing the results for various gate areas.

Paper Details

Date Published: 13 September 1996
PDF: 8 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250869
Show Author Affiliations
Katsuhiko Kubota, Hitachi, Ltd. (Japan)
C. Suzuki, Hitachi, Ltd. (Japan)
Kosuke Okuyama, Hitachi, Ltd. (Japan)
N. Suzuki, Hitachi, Ltd. (Japan)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

© SPIE. Terms of Use
Back to Top