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Proceedings Paper

Optimizing a manufacturing submicron CMOS process for low-voltage applications
Author(s): Jun Ma; Sunny Cheng; Bob Pryor; Kevin Klein
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Paper Abstract

A low threshold voltage (Vt) is desired to improve a CMOS circuit performance when operating at reduced supply voltages to save power. In this paper, a practical approach to reduce Vt for a conventional, manufacturing submicron CMOS process is presented. This `evolutionary' approach to reduce Vt is taken so as the ensure manufacturability and to reduce process cost. This is found to be useful especially before a deep-submicron or a sophisticated process targeted for low voltage application becomes available and manufacturable. Vt reduction is achieved by the integration of a thinner, in the case presented here a 105 angstroms, gate oxide into a 0.65 micrometers process. The process is then optimized to provide the device with highest current-drive while obtaining lowest Vt with acceptable subthreshold leakage with conventional front-end and back-end process. It is shown that, with the minimal changes to the 0.65 micrometers conventional manufacturing process, the Vt's for nominal n- and p-channel devices can be reduced by 20% - 30%, with more than 1.5X improvement in current drive at 3.3 V compared to devices with 150 angstroms gate oxide. The enhancement of circuit performance is demonstrated with measurements of benchmark circuits including CPU, ROM, and FSRAM, where successful operation has been obtained near IV and operating frequencies are nearly doubled at supply voltage near 1.6 V compared to conventional 0.65 micrometers process.

Paper Details

Date Published: 13 September 1996
PDF: 6 pages
Proc. SPIE 2875, Microelectronic Device and Multilevel Interconnection Technology II, (13 September 1996); doi: 10.1117/12.250857
Show Author Affiliations
Jun Ma, Motorola (United States)
Sunny Cheng, Motorola (United States)
Bob Pryor, Motorola (United States)
Kevin Klein, Motorola (United States)


Published in SPIE Proceedings Vol. 2875:
Microelectronic Device and Multilevel Interconnection Technology II
Ih-Chin Chen; Nobuo Sasaki; Divyesh N. Patel; Girish A. Dixit, Editor(s)

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