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Proceedings Paper

Wire length and via reduction for yield enhancement
Author(s): Venkat K. R. Chiluvuri; Israel Koren
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Paper Abstract

Wire length reduction along with via minimization results in better performance and higher yield for VLSI circuits. In this paper we present a wire length reduction algorithm for channel routing. The results of our algorithm for a set of benchmark examples are presented. The algorithm produces near optimal results for most of the examples. Surprisingly, our algorithm outperforms most of the previously proposed via minimization algorithms as well. Our results show that both wire length and via minimization problems are closely related to each other but their optimal solutions don't necessarily coincide.

Paper Details

Date Published: 12 September 1996
PDF: 9 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250850
Show Author Affiliations
Venkat K. R. Chiluvuri, Motorola (United States)
Israel Koren, Univ. of Massachusetts/Amherst (United States)

Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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