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Proceedings Paper

Plasma-induced oxide contamination in a 0.35-um CMOS process
Author(s): Martin P. Karnett; Jingrong Zhou; Sumanta Ghosh; Danny Echtle; L. Fritz; Martin Manley; Gregory S. Scott
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Paper Abstract

Plasma contamination in a 0.35 micrometer triple-level metal CMOS process was investigated in response to anomalous dc parametric test data. Electrical PMOS transistor performance and both physical and electrical gate oxide thickness were significantly degraded upon exposure of a sacrificial oxide to a plasma ash following a masked, P-channel threshold adjust ion implant. The contamination was isolated to a specific asher, found to be radial in nature across a wafer, and consistently worse in one of the two chambers used during the ash process. The contamination dramatically reduced the wet etch rate of the sacrificial oxide, leading to incomplete removal prior to gate oxide growth. Increasing the wet strip time of the sacrificial oxide improved the ability to remove this contaminated film, but was limited by minimal field oxide thickness requirements to avoid field inversion. Transferring the ash process to an alternative, low-damage, down-stream asher eliminated the plasma contamination.

Paper Details

Date Published: 12 September 1996
PDF: 5 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250843
Show Author Affiliations
Martin P. Karnett, VLSI Technology, Inc. (United States)
Jingrong Zhou, VLSI Technology, Inc. (United States)
Sumanta Ghosh, VLSI Technology, Inc. (United States)
Danny Echtle, VLSI Technology, Inc. (United States)
L. Fritz, VLSI Technology, Inc. (United States)
Martin Manley, VLSI Technology, Inc. (United States)
Gregory S. Scott, VLSI Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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