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Proceedings Paper

Fault isolation with fanin tree technique
Author(s): Kang Siong Ng
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Paper Abstract

With the ever increasing complexity in IC design and with the introduction of flip chip technology, the pressing need for computer aided fault isolation (FI) is sensed. Fanin tree is a collection of subsequent fan-in signals with respect to a given node. As such, possible failing locations can be narrowed down to nodes that reside within the fanin tree only. Multiple fanin trees from multiple known failing nodes can also be intersected to locate common driving nodes. This paper presents an application program that was developed for Intel standard (.sch) netlist format. The result is FTREE; a fanin tree tool that is independent of product. This tool enhances the performance of other FA tools; but for its optimum usage, proper scan node selection is required during design stage. Selection of these nodes also is presented.

Paper Details

Date Published: 12 September 1996
PDF: 6 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250838
Show Author Affiliations
Kang Siong Ng, Intel Technology Sdn. Bhd. (Malaysia)

Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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