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Proceedings Paper

Reliability issue on pipeline defects in CMOS memory devices
Author(s): So Youn; Kyle Terrell; Chau-Chin Wu; Paul Shy; Chuen-Der Lien
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Paper Abstract

Pipeline defects have recently been reported in a leakage source of CMOS devices when die shrink. We report the observed physical defects which shorted source and drain under .6 u short channel CMOS devices by the Wright-etching of the defective devices. We also found pipeline defects filled with phosphorous doped n-type material by the cross- sectioning of the pipeline in the channel of NMOS transistor. We also observed that devices are failing during high temperature reliability test, which causes single bit failure. This indicates that there are many potential defective die to reach assembly process even though most of detectives are discarded at wafer sort. SEM analysis identifies that location of defective parts is decorated with a pair of protruding holes at the 90 degree corner of field island of faulty pass-gate of SRAM. These pipeline defects are caused mainly by the compressed stress from field oxide. Reliability and yield have been improved since the pipeline were minimized after relieving stress on pass- gate.

Paper Details

Date Published: 12 September 1996
PDF: 8 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250837
Show Author Affiliations
So Youn, Integrated Devices Technology, Inc. (United States)
Kyle Terrell, Integrated Devices Technology, Inc. (United States)
Chau-Chin Wu, Integrated Devices Technology, Inc. (United States)
Paul Shy, Integrated Devices Technology, Inc. (United States)
Chuen-Der Lien, Integrated Devices Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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