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Proceedings Paper

Inter- and intra-die polysilicon critical dimension variation
Author(s): Brian Stine; Duane S. Boning; James E. Chung; David A. Bell; Edward Equi
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Paper Abstract

A methodology has been developed as part of a statistical metrology framework (1) to assess the relative range and distribution of intra-die, or die-level, polysilicon critical dimension variation as opposed to wafer-level, or inter-die, poly-CD variation; (2) to identify the key layout factors involved in poly-CD intra-die variation; and (3) to develop first-order semi-empirical models for poly-CD variation. A new approach utilizing multivariate analysis of variance methods is described to model the die- and wafer- level variation components. We show that pattern dependent variation is approximately twice as large as wafer-level variation. In addition, we find that spatial position plays a strong role: the first-order pattern dependent variation model (or die 'signature') shows a strong dependence on spatial position across the wafer, and individual components of the model demonstrate different spatial position sensitivities.

Paper Details

Date Published: 12 September 1996
PDF: 9 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250826
Show Author Affiliations
Brian Stine, Massachusetts Institute of Technology (United States)
Duane S. Boning, Massachusetts Institute of Technology (United States)
James E. Chung, Massachusetts Institute of Technology (United States)
David A. Bell, Digital Equipment Corp. (United States)
Edward Equi, Digital Equipment Corp. (United States)


Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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