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Proceedings Paper

Design of the UltraSPARC-I microprocessor for manufacturing performance
Author(s): Lynn Youngs; Greg Billus; Anjali Jones; Siva Paramanandam
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Paper Abstract

The 5.2 M transistor UltraSPARC(TM)-I microprocessor is manufactured using the 0.5 micrometer EPIC3 CMOS QLM process. Design features were implemented to accelerate increases in manufacturing yield and product performance while enabling rapid establishment of high-coverage manufacturing test. Support for production memory defect mapping and repair, scan-based testing and failure analysis, component identity tracking, Iddq testing, per-chip CMOS process parameter monitoring, and aggressive process scalability were included. In implementing these features, our goal was to build a foundation for automatic and continuous identification of bottlenecks in performance of the overall microprocessor manufacturing process.

Paper Details

Date Published: 12 September 1996
PDF: 8 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250825
Show Author Affiliations
Lynn Youngs, Texas Instruments Inc. (United States)
Greg Billus, Texas Instruments Inc. (United States)
Anjali Jones, Texas Instruments Inc. (United States)
Siva Paramanandam, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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