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Proceedings Paper

Fast failure analysis and yield enhancement: an integrated approach
Author(s): Fourmun Lee; Nam Doan; Lisa H. Liu
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Paper Abstract

This paper describes the integrated fast failure analysis/yield enhancement system used at Motorola's MOS-12 fab, established with the goal of providing high speed diagnostics and feedback. This goal was achieved through tight integration of in-fab inspection tools with electrical test equipment, out-of-fab analytical tools, and software tools. At this facility, the use of common file formats permits data exchange between wafer inspection tools, optical review stations, SEM, FIB, and electrical work bench testers. Wafer images generated at all diagnostic tools are stored on a video archival/retrieval system (VARSTM). Correlation is a powerful tool for reducing failure analysis time and increasing failure analysis efficiency. By overlaying in-line inspection data with process, parametric, sort bin, and bitmap data, the locations of potential killer defects are rapidly identified. Physical failure analysis is performed on selected correlated failures to confirm the cause of device failures. Using analytical instruments with full wafer capability, in-line inspection or bitmap information are used to quickly locate the defects of interest. This approach has been successfully used to significantly reduce FA time compared with traditional FA methods. Fast failure analysis/yield enhancement is demonstrated with three case studies.

Paper Details

Date Published: 12 September 1996
PDF: 10 pages
Proc. SPIE 2874, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II, (12 September 1996); doi: 10.1117/12.250818
Show Author Affiliations
Fourmun Lee, Motorola (United States)
Nam Doan, Motorola (United States)
Lisa H. Liu, Motorola (United States)


Published in SPIE Proceedings Vol. 2874:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis II
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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