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Proceedings Paper

VHDL-based parameterized clock manager simulator for FPGA
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Paper Abstract

The article discusses a method of building a universal, parameterized clock management module for the process of functional simulation. The solution was designed for various families of FPGA circuits and popular VHDL compilers. The algorithm for automatic module configuration for given parameters of output clocks and method of synchronization with the reference clock are discussed. The basic solution implemented in the VHDL language in a behavioral form and selected examples of practical use for complex clock signal relations are presented in detail.

Paper Details

Date Published: 1 October 2018
PDF: 10 pages
Proc. SPIE 10808, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2018, 108083Y (1 October 2018); doi: 10.1117/12.2501465
Show Author Affiliations
Krzysztof T. Pozniak, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 10808:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2018
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)

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