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Symmetric block encoder based on reversible circuits
Author(s): Marek Pawłowski; Zbigniew Szymański
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Paper Abstract

The goal of the presented work is a project of a novel symmetric block encoder. The basic processing elements are cascades of reconfigurable reversible gates changing the type of gates depending on the encryption key. The presented solution proposes the use of sixteen 8-bit cascades, which configuration requires a 640-bit key. The input information is processed in five rounds. The encryption keys in the subsequent rounds differ. The design was modeled in VHDL language and placed in an FPGA chip. The project is scalable, i.e. depending on the needs, it can be modified by changing the number of gates in the cascade, the width of the information block being processed, which may result in an increase or decrease in the width of the encryption key. The number of rounds may also be modified. The large size of the encryption key should ensure the safety of the encrypted data.

Paper Details

Date Published: 1 October 2018
PDF: 7 pages
Proc. SPIE 10808, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2018, 108081V (1 October 2018); doi: 10.1117/12.2501438
Show Author Affiliations
Marek Pawłowski, Warsaw Univ. of Technology (Poland)
Zbigniew Szymański, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 10808:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2018
Ryszard S. Romaniuk; Maciej Linczuk, Editor(s)

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