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Proceedings Paper

Instruction systolic array in image processing applications
Author(s): Manfred Schimmler; Hans-Werner Lang
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Paper Abstract

The ISATEC parallel computer is the first implementation of an instruction systolic array for the commercial market. The goal i\of integration of 1024 processors on an add-on-board for PCs has been achieved by the development of a low- power/low-area processor architecture whose instruction set is suited particularly for image processing applications. The paper introduces the concept of the instruction systolic array, its implementation and some application examples in the field of image processing.

Paper Details

Date Published: 21 August 1996
PDF: 9 pages
Proc. SPIE 2784, Vision Systems: Sensors, Sensor Systems, and Components, (21 August 1996); doi: 10.1117/12.248524
Show Author Affiliations
Manfred Schimmler, ISATEC Soft- und Hardware GmbH (Germany)
Hans-Werner Lang, Fachhochschule Flensburg (Germany)

Published in SPIE Proceedings Vol. 2784:
Vision Systems: Sensors, Sensor Systems, and Components
Otmar Loffeld, Editor(s)

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