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Proceedings Paper

Parallel architecture dedicated to image component labeling in O(n Log n): FPGA implementation
Author(s): Eril Mozef; Serge Weber; Jamal Jaber; Gerard Prieur
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Paper Abstract

Connected component labelling is sa fundamental task in intermediate level vision. Current research points to parallel architecture as an excellent solution in response to this problem. In order to exploit a global approach while optimizing the electronic structure and minimizing data propagation, a parallel architecture dedicated to image component labeling is envisages. For an n by n image, the optimized architecture merely requires n/2-1 PE's and n2/4 CAM (content addressable memory) modules through a 4 pixels grouping technique. The global communication is reconfigurable and ensured in O(log n) units of propagation time by a tree structure of switches. Moreover, a PE permits sequential processing in its memories array, perfectly adapted to labeling from any interlaced-mode video signal. In this mode, the architecture permits labeling in one scan image while simultaneously loading the image. The proposed algorithm, based on a divide-and-conquer technique, leads to a complexity of O(n log n) with a small constant multiplicative factor. We discuss the simulation results, the possibility of FPGA implementation and of development of this architecture.

Paper Details

Date Published: 21 August 1996
PDF: 6 pages
Proc. SPIE 2784, Vision Systems: Sensors, Sensor Systems, and Components, (21 August 1996); doi: 10.1117/12.248522
Show Author Affiliations
Eril Mozef, LIEN/Univ. de Nancy I (France)
Serge Weber, LIEN/Univ. de Nancy I (France)
Jamal Jaber, LIEN/Univ. de Nancy I (France)
Gerard Prieur, LIEN/Univ. de Nancy I (France)


Published in SPIE Proceedings Vol. 2784:
Vision Systems: Sensors, Sensor Systems, and Components

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