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Proceedings Paper

On-focal-plane ADC: recent progress at JPL
Author(s): Zhimin Zhou; Bedabrata Pain; Roger Panicacci; Karmak Mansoorian; Junichi Nakamura; Eric R. Fossum
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Paper Abstract

Two 8 bit successive approximation analog-to-digital converters (ADC), an 8 bit single slope ADC and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The 20.4 micrometers and 40 micrometers pitch successive approximation test chip designs are compatible with active pixel sensors (APS) column parallel architectures. A 64 X 64 photogate APS with this ADC integrated on-chip was fabricated in a 1.2 micrometers N-well CMOS process and achieves 8 bit accuracy. A 1 K X 1 K APS with 11 micrometers pixels and a single slope ADC in each column was fabricated in a 0.55 micrometers N-well CMOS process and also achieves 8 bit accuracy. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. It consumes 800 (mu) W at a 5 KHz conversion rate.

Paper Details

Date Published: 26 June 1996
PDF: 12 pages
Proc. SPIE 2745, Infrared Readout Electronics III, (26 June 1996); doi: 10.1117/12.243529
Show Author Affiliations
Zhimin Zhou, Jet Propulsion Lab. (United States)
Bedabrata Pain, Jet Propulsion Lab. (United States)
Roger Panicacci, Jet Propulsion Lab. (United States)
Karmak Mansoorian, Jet Propulsion Lab. (United States)
Junichi Nakamura, Olympus America Inc. (United States)
Eric R. Fossum, Jet Propulsion Lab. (United States)

Published in SPIE Proceedings Vol. 2745:
Infrared Readout Electronics III
Eric R. Fossum, Editor(s)

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