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Proceedings Paper

Readout concept employing a novel on-chip 16-bit ADC for smart IR focal plane arrays
Author(s): Ulf Ringh; Christer Jansson; Kevin Charles Liddiard
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Paper Abstract

This paper discusses CMOS readout for an uncooled 2D IR array of resistance bolometers. Factors influencing the architectural choice and detailed noise considerations for the pixel select switch are covered. A parallel readout concept using one ADC per column is the suggested architecture for an uncooled CMOS IR array. In order to meet the requirement on speed and resolution a new ADC principle had to be developed. The ADC is however of general interest where resolution above 10 bits at medium speed and low cost are desired. High linearity is obtained utilizing the first- order delta-sigma converter technique, while resolution and speed is enhanced by a successive approximation of the delta-sigma integrator residual voltage. An experimental 16 X 16 infrared bolometer detector array has been designed where a row-by-row readout operation of the bolometer array is supported by a column-wise 16-bit A/D conversion. The 16- column preamplifiers and ADC structure has been implemented in a standard 0.8 micrometers CMOS process with 40 micrometers column pitch. Measured results of the experimental array is presented, including both electronics and detectors.

Paper Details

Date Published: 26 June 1996
PDF: 12 pages
Proc. SPIE 2745, Infrared Readout Electronics III, (26 June 1996); doi: 10.1117/12.243528
Show Author Affiliations
Ulf Ringh, National Defence Research Establishment (Sweden)
Christer Jansson, National Defence Research Establishment (Sweden) and Linkoping Univ. (Sweden)
Kevin Charles Liddiard, Defence Science and Technology Organisation (Australia)


Published in SPIE Proceedings Vol. 2745:
Infrared Readout Electronics III
Eric R. Fossum, Editor(s)

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