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Proceedings Paper

VLSI architecture and implementation of a multifunction, forward/inverse discrete cosine transform processor
Author(s): Masanori Maruyama; H. Uwabu; I. Iwasaki; Hiroshi Fujiwara; Toshifumi Sakaguchi; Ming-Ting Sun; Ming Lei Liou
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Paper Abstract

The Discrete Cosine Transform (DCT) is considered to be the most effective transfonn coding technique for image and video compression. In this paper a new implementation of an experimental prototype multi-function DCT/IDCT (Inverse DCT) chip is reported. The chip is based on a distributed arithmetic architecture. The main features of the chip include: 1) The DCT and the IDCT are integrated in the same chip 2) the chip achieves high accuracy exceeding the stringent requirements of a proposed CCITF standard 3) it achieves a high operating speed of 27 MHz and is thus applicable to a wide-range of real-time image and video applications 4) the internal clock frequency is the same as the pixel rate and 5) with an on-chip zigzag scan converter and an adder/subtractor it is multifunctional and useful in a DPCM configuration. The chip is implemented with standard cells and contains about 156k transistors.

Paper Details

Date Published: 1 September 1990
PDF: 8 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24228
Show Author Affiliations
Masanori Maruyama, Graphic Communication Technologies, Ltd. (Japan)
H. Uwabu, Graphic Communication Technologies, Ltd. (Japan)
I. Iwasaki, Graphic Communication Technologies, Ltd. (Japan)
Hiroshi Fujiwara, Graphic Communication Technologies, Ltd. (Japan)
Toshifumi Sakaguchi, Graphic Communication Technologies, Ltd. (Japan)
Ming-Ting Sun, Bell Communications Research (United States)
Ming Lei Liou, Bell Communications Research (United States)


Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

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