Share Email Print

Proceedings Paper

VLSI-architectures for the hierarchical block-matching algorithm for HDTV applications
Author(s): Luc P.L. De Vos
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper describes VLSI-architectures for HDTV-suitable implementations of two well-known hierarchical block-matching algorithms: the three-step search algorithm and the one-at-a-time search algorithm. The architectures exploit the regularity and design efficiency of systolic arrays, combined with a decision-driven on-chip data handling. They are capable of treating (16*16)-blocks, with a maximum displacement of +/-14 pixels, at 50MHz pixel rate. Another important feature is the small input-data bandwidth, which keeps to a minimum the requirements to external memory units. Transistor count and chip area estimations show that the architectures can be realized with today's CMOS technologies.

Paper Details

Date Published: 1 September 1990
PDF: 12 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24227
Show Author Affiliations
Luc P.L. De Vos, Siemens AG (Germany)

Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

© SPIE. Terms of Use
Back to Top