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Proceedings Paper

Analog parallel processor hardware for high-speed pattern recognition
Author(s): Taher Daud; Raoul Tawel; Harry Langenbacher; Silvio P. Eberhardt; Anilkumar P. Thakoor
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Paper Abstract

We report on a VLSI-based analog processor for fully parallel, associative, high-speed pattern matching. The processor consists of two main components: one, an analog memory matrix for storage of a library of patterns, and the other, a winner- take-all (WTA) circuit for selection of the stored pattern that best matches an input pattern. An inner product is generated between the input vector and each of the stored memories. The resulting values are applied in parallel to a WTA network for determination of the closest match. Patterns with up to 22% overlap are successfully classified with a WTA settling time of less than 10|is. Applications such as star pattern recognition and mineral classification with bounded overlap patterns have been successfully demonstrated. This architecture has a potential for an overall pattern matching speed in excess of 109 bits per second for a large (32-bit x 1000-pattern) memory.

Paper Details

Date Published: 1 September 1990
PDF: 12 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24223
Show Author Affiliations
Taher Daud, Jet Propulsion Lab. (United States)
Raoul Tawel, Jet Propulsion Lab. (United States)
Harry Langenbacher, Jet Propulsion Lab. (United States)
Silvio P. Eberhardt, Jet Propulsion Lab. (United States)
Anilkumar P. Thakoor, Jet Propulsion Lab. (United States)


Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

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