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Proceedings Paper

CCD focal-plane real-time image processor
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Paper Abstract

A focal-plane-array chip designed for real-time, general-purpose, image preprocessing is reported. A 48 X 48 pixel detector array and a 24 X 24 processing element processor array are monolithically integrated on the chip. The analog, charge-coupled device-based VLSI chip operates in the charge domain and has sensing, storing, and computing capabilities. The chip was fabricated with a double-poly, double-metal process in a commercial CCD foundry. The simulation of an edge detection algorithm implemented by the chip is presented. An overview of the chip performance is described as well.

Paper Details

Date Published: 1 September 1990
PDF: 5 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24219
Show Author Affiliations
Sayed I. Eid, Columbia Univ. (United States)
Eric R. Fossum, Columbia Univ. (United States)


Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

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