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Proceedings Paper

TM-66 swiFFT DSP chip: architecture, algorithms, and applications
Author(s): John A. Marsh; John McCaskill
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Paper Abstract

This paper discusses the architectures of the TM-66 swiFFT DSP chip, the algorithms that the swiFFT chip is optimized for, the design of the S2 vector processing node that uses it, and applications of the above. The architecture of the swiFFT chip is optimized for real-time DSP processing in general, and the FFT algorithm in particular. It uses twenty IEEE 32-bit floating point adders and multipliers to sustain 680 MFLOPS during FFT processing and other algorithms, making it one of the fastest floating point DSP chips generally available. This paper discusses in detail the internal architecture, the tradeoffs between performance and generality, and the implementation of the FFT and other algorithms using this chip. In conclusion, some brief design overviews of a dual TM-66 board and an FFT building-block module are given to illustrate data flow through, and control of, the TM-66 swiFFT chip.

Paper Details

Date Published: 7 June 1996
PDF: 11 pages
Proc. SPIE 2750, Digital Signal Processing Technology, (7 June 1996); doi: 10.1117/12.241991
Show Author Affiliations
John A. Marsh, Texas Memory Systems, Inc. (United States)
John McCaskill, Texas Memory Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 2750:
Digital Signal Processing Technology
Joseph Picone, Editor(s)

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