Share Email Print
cover

Proceedings Paper

Optimization of i-line resist process for 0.5-μm polysilicon gate structures using a top-coat layer
Author(s): Jean-Paul E. Chollet; Marie-Therese Basso
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

For the manufacturing of 0.5 micrometer devices and below, the control of the gate CD must be accurate to guarantee the yield of circuits. To overcome the swing curve effect, a dyed resist gives a partial answer. The profiles and the resolution of the resist are decreased. The reduction of swing curve is not adequate. A top antireflective coating (TARC) is a recent industrial solution. The process is not complex, the throughput is maintained and there is not a modification of the hardware of the track. The thickness of the resist coated over the topography (LOCOS 250 nm) is however not equal. Consequently, the thickness of the TARC AQUATAR must be adjusted to 64 nm over topography to the minimum swing ratio (R1 reduced to zero). This paper studies the influence of the thickness of AQUATAR and the thickness of the resist on the final CD after etching over topography. To minimize the CD range of gate structure due to swing curve effect it is found necessary to modify the thickness of top arc from 64 nm to 45 nm over topography.

Paper Details

Date Published: 14 June 1996
PDF: 7 pages
Proc. SPIE 2724, Advances in Resist Technology and Processing XIII, (14 June 1996); doi: 10.1117/12.241873
Show Author Affiliations
Jean-Paul E. Chollet, France Telecom/CNET (France)
Marie-Therese Basso, France Telecom/CNET (France)


Published in SPIE Proceedings Vol. 2724:
Advances in Resist Technology and Processing XIII
Roderick R. Kunz, Editor(s)

© SPIE. Terms of Use
Back to Top