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Proceedings Paper

Principal devices and hardware volume estimation for moving picture decoder for digital storage media
Author(s): Makiko Konoshima; Osamu Kawai; Kiichi Matsuda
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Paper Abstract

The ISO/MPEG has been discussing the establishment of a standard for moving- picture coding to ensure that digital storage media can store picture information efficiently. This paper introduces a trial design for the source decoder of simulation model 2 in the ISO/MPEG video subgroup. This paper describes MPEG simulation model decoding and the Fujitsu video signal processors, VSP-1 and DCT LSI chips. We designed a source decoder using these two LSI chips, memory, and standard logic ICs. The trial design showed that three VSP-ls and one DCT LSI chips are sufficient to make a source decoder.

Paper Details

Date Published: 1 September 1990
PDF: 9 pages
Proc. SPIE 1360, Visual Communications and Image Processing '90: Fifth in a Series, (1 September 1990); doi: 10.1117/12.24171
Show Author Affiliations
Makiko Konoshima, Fujitsu Labs. Ltd. (Japan)
Osamu Kawai, Fujitsu Labs. Ltd. (Japan)
Kiichi Matsuda, Fujitsu Labs. Ltd. (Japan)

Published in SPIE Proceedings Vol. 1360:
Visual Communications and Image Processing '90: Fifth in a Series
Murat Kunt, Editor(s)

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