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Proceedings Paper

Integrated process for smart microstructures
Author(s): Tao Pan; Jeffery M. Melzak; Steven Garverick; Mehran Mehregany
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Paper Abstract

An eight-mask integrated process for smart microstructures is presented, based on an enhancement-depletion NMOS circuit process and a two-layer polysilicon surface micromachining process. Design and fabrication issues, such as circuit encapsulation, interconnect, and thermal budget are addressed. Two types of micromechanical structures, microcantilever beams and shear stress sensors, were fabricated with on-chip signal conditioning circuits. Electrical test results on circuitry both integrated and not integrated with micromechanisms are discussed. Electromechanical test data demonstrating the resonant frequency of integrated microcantilever beam structures is presented as well as calibrated flow channel data for micromachined shear stress sensors.

Paper Details

Date Published: 20 May 1996
PDF: 13 pages
Proc. SPIE 2722, Smart Structures and Materials 1996: Smart Electronics and MEMS, (20 May 1996); doi: 10.1117/12.240432
Show Author Affiliations
Tao Pan, Case Western Reserve Univ. (United States)
Jeffery M. Melzak, Case Western Reserve Univ. (United States)
Steven Garverick, Case Western Reserve Univ. (United States)
Mehran Mehregany, Case Western Reserve Univ. (United States)


Published in SPIE Proceedings Vol. 2722:
Smart Structures and Materials 1996: Smart Electronics and MEMS
Vijay K. Varadan; Paul J. McWhorter, Editor(s)

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