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Proceedings Paper

Wafer flatness modeling for scanning steppers
Author(s): Randal K. Goodall; Howard R. Huff
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Paper Abstract

Model-based analysis is used to explain previous observations regarding the distributional form and numeric relationships of several key lithographic flatness quality metrics for silicon wafers. The dominant relationships are controlled by longer wavelength (tens of millimeters) surface topography, while the distribution shapes are controlled by shorter wavelength (few millimeters) topography. A lithographic flatness modeling framework is introduced which can provide guidance for specification of silicon wafer flatness for ULSI IC products. New site flatness models show that, compared to a full-field stepper, a scanning stepper can effect improved flatness performance from wafers of similar quality.

Paper Details

Date Published: 21 May 1996
PDF: 9 pages
Proc. SPIE 2725, Metrology, Inspection, and Process Control for Microlithography X, (21 May 1996); doi: 10.1117/12.240143
Show Author Affiliations
Randal K. Goodall, International 300 mm Initiative (United States)
Howard R. Huff, SEMATECH (United States)


Published in SPIE Proceedings Vol. 2725:
Metrology, Inspection, and Process Control for Microlithography X
Susan K. Jones, Editor(s)

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