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Proceedings Paper

Electrical test structures replicated in silicon-on-insulator material
Author(s): Michael W. Cresswell; Jeffry J. Sniegowski; Rathindra N. Ghoshtagore; Richard A. Allen; Loren W. Linholm; John S. Villarrubia
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Paper Abstract

Measurements of the linewidths of submicrometer features made by different metrology techniques have frequently been characterized by differences of up to 90 nm. The purpose of the work reported here is to address the special difficulties that this phenomenon presents to the certification of reference materials for the calibration of linewidth-measurement instruments. Accordingly, a new test structure has been designed and fabricated, and has undergone preliminary tests. Its distinguishing characteristics are assured cross-sectional profile geometries with known side-wall slopes, surface planarity, and compositional uniformity when it is formed in mono-crystalline material at selected orientations to the crystal lattice. To allow the extraction of electrical linewidth, the structure is replicated in a silicon film of uniform conductivity which is separated from the silicon substrate by a buried oxide layer. The utilization of a silicon-on-insulator (SOI) substrate further allows the selective removal of substrate material from local regions below the reference features, thus facilitating measurements by optical and electron-beam transmission microcopy. The combination of planar feature surfaces having known side-wall slopes is anticipated to eliminate factors which are believed to be responsible for methods divergence in linewidth measurements, a capability which is a prerequisite for reliable certification of the linewidths of features on reference materials.

Paper Details

Date Published: 21 May 1996
PDF: 18 pages
Proc. SPIE 2725, Metrology, Inspection, and Process Control for Microlithography X, (21 May 1996); doi: 10.1117/12.240117
Show Author Affiliations
Michael W. Cresswell, National Institute of Standards and Technology (United States)
Jeffry J. Sniegowski, Sandia National Labs. (United States)
Rathindra N. Ghoshtagore, National Institute of Standards and Technology (United States)
Richard A. Allen, National Institute of Standards and Technology (United States)
Loren W. Linholm, National Institute of Standards and Technology (United States)
John S. Villarrubia, National Institute of Standards and Technology (United States)


Published in SPIE Proceedings Vol. 2725:
Metrology, Inspection, and Process Control for Microlithography X
Susan K. Jones, Editor(s)

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