Share Email Print
cover

Proceedings Paper

Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors
Author(s): Roger Panicacci; Bedabrata Pain; Zhimin Zhou; Junichi Nakamura; Eric R. Fossum
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 micrometers pitch in a 1.2 micrometers n-well CMOS process and a 40 micrometers pitch in a 2 micrometers n-well CMOS process. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 (mu) W at a 5 KHz conversion rate.

Paper Details

Date Published: 25 March 1996
PDF: 9 pages
Proc. SPIE 2654, Solid State Sensor Arrays and CCD Cameras, (25 March 1996); doi: 10.1117/12.236120
Show Author Affiliations
Roger Panicacci, Jet Propulsion Lab. (United States)
Bedabrata Pain, Jet Propulsion Lab. (United States)
Zhimin Zhou, Jet Propulsion Lab. (United States)
Junichi Nakamura, Olympus America Inc. (United States)
Eric R. Fossum, Jet Propulsion Lab. (United States)


Published in SPIE Proceedings Vol. 2654:
Solid State Sensor Arrays and CCD Cameras
Constantine N. Anagnostopoulos; Morley M. Blouke; Michael P. Lesser, Editor(s)

© SPIE. Terms of Use
Back to Top