Share Email Print

Proceedings Paper

Efficient VLSI algorithm and an implementation architecture for gray-scale morphology
Author(s): Sung-Jea Ko; Malayappan Shridhar
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents an efficient VLSI architecture for the real-time implementation of grayscale morphological operations. The proposed architecture employs a bit-serial approach which allows grayscale morphological operations to be decomposed into bit-level binary operations by a bit-modification algorithm, and thus requires only p binary operation units for the p-bit grayscale signal. In this realization, grayscale opening and closing are accomplished by local rather than cascade operations, providing greatly increased data throughput. It is shown that this realization is simple and modular in structure and is suitable for VLSI implementation.

Paper Details

Date Published: 1 November 1990
PDF: 11 pages
Proc. SPIE 1350, Image Algebra and Morphological Image Processing, (1 November 1990); doi: 10.1117/12.23604
Show Author Affiliations
Sung-Jea Ko, Univ. of Michigan/Dearborn (United States)
Malayappan Shridhar, Univ. of Michigan/Dearborn (United States)

Published in SPIE Proceedings Vol. 1350:
Image Algebra and Morphological Image Processing
Paul D. Gader, Editor(s)

© SPIE. Terms of Use
Back to Top