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Proceedings Paper

Time-space modal logic for verification of bit-slice circuits
Author(s): Hiromi Hiraishi
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Paper Abstract

The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

Paper Details

Date Published: 22 March 1996
PDF: 6 pages
Proc. SPIE 2644, Fourth International Conference on Computer-Aided Design and Computer Graphics, (22 March 1996); doi: 10.1117/12.235564
Show Author Affiliations
Hiromi Hiraishi, Kyoto Sangyo Univ. (Japan)


Published in SPIE Proceedings Vol. 2644:
Fourth International Conference on Computer-Aided Design and Computer Graphics

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